Difference: MassStorage (12 vs. 13)

Revision 132019-02-02 - PeterSchmid

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EEPROM patched on MC PCB

EEPROM patched on MC PCB

Changed:
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SPI Mode 0, data is always latched in on the rising edge of SCK and always output on the falling edge of SCK. For CS one output port bis is needed e.g. O7 or N2 (INP4) to start/end operation (A high-to-low transition on the CS pin is required to start an operation and a low-to-high transition is required to end an operation).
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SPI Mode 0, data is always latched in on the rising edge of SCK and always output on the falling edge of SCK. For CS one output port bis is needed e.g. O7 or N0 (INP1) to start/end operation (A high-to-low transition on the CS pin is required to start an operation and a low-to-high transition is required to end an operation).
 
SPI MC (Master) 25LCxxxx (Slave) Interface
MISO EF2 2 SO direct
MOSI D0 5 SI direct
CLK TPB & N1 (OUT2) 6 SCK wired AND; Pullup 10 k, 2 1N4148
Changed:
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CS N2 1 CS direct
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CS N0 1 CS direct
 
    8 VCC +5V
    3 WP +5V
  J2.14 WAIT 7 HOLD direct
 
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