Difference: McForth (14 vs. 15)
Revision 152019-01-19 - PeterSchmid
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| Sharing the LED and Switch port, you loose two LEDs and one switch. Possible conflict with the bootstrap loader, if there is a read sequence (CS and read pattern 0000 0011). To prevent this, set the EEPROM into HOLD state e.g. with the WAIT/ signal. | |||||||||||||
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| SPI Mode 0, data is always latched in on the rising edge of SCK and always output on the falling edge of SCK. For CS one output port bis is needed e.g. O7. | |||||||||||||
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| OUT2,0b00000000 ; CLK for SPI with data bit cleared LSDF OUT2,0b00000001 ; CLK for SPI with data bit set | |||||||||||||
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| DEC R6 GLO R6 BNZ BITLOOP | |||||||||||||
View topic | History: r25 < r24 < r23 < r22 | More topic actions...
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