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%DASHBOARD{ section="banner" | ||||||||
Line: 27 to 27 | ||||||||
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< < | Concatenated this two files as mc-forth.hex and convert it to a binary file: | |||||||
> > | Concatenate this two files as mc-forth.hex and convert it to a binary file: | |||||||
pi@cosmac:~/elf/forth $ cat idiot_new_qhi.hex forth.hex > mc-forth.hex pi@cosmac:~/elf/forth $ hex2bin mc-forth.hex | ||||||||
Line: 154 to 154 | ||||||||
C-H Ting, Juergen Pintaske and Steve Teal wrote the fine book
FIG-Forth Manual: Documentation and Test in 1802 IP![]() | ||||||||
Changed: | ||||||||
< < | I bought the book and the proposed Lattice FPGA board ICE40HX8K-B-EVN | |||||||
> > | I bought the book and the proposed Lattice FPGA board ICE40HX8K-B-EVN | |||||||
(e.g. from mouser, about $50). This FPGA can be programmed as an CDP1802 system with RAM, UART, Timer and I/O, the serial console is also implemented as USB CDC! | ||||||||
Line: 194 to 194 | ||||||||
?TERMINAL does not seem to work as expected. | ||||||||
Changed: | ||||||||
< < | The system on chip coded in VHDL and implemented for the Lattice iCE40-hx8k dev board is about 150 times faster than the Membership Card. That's about 300 MHz clock for an original CDP1802. | |||||||
> > | The system on chip coded in VHDL and implemented for the Lattice iCE40-hx8k dev board is about 150 times faster than the Membership Card. That's about 300 MHz clock for an original CDP1802. | |||||||